The present invention relates, in general, to the field of phase-locked loop (PLL) clocking circuits. More particularly, the present invention relates to a PLL fail-over circuit technique and method to mitigate the effects of single-event transients.
Energetic particle strikes leading to single-event transients (SETs) are an increasing concern for digital circuits encountering radiation environments. As device geometries become ever more reduced in size, they exhibit a concomitantly greater sensitivity to such SETs which can induce the generation of transients in the device leading to errors propagating through the system.
As data rates and processing speeds increase the need for stable, low jitter, phase-locked loop clocking sources is becoming increasingly more important. Systems exposed to harsh environments require highly reliable clock sources to ensure correct operation of critical systems. Single-event transient phenomena can cause more than just clocking errors in PLLs that negatively affect bit error rates and such phenomena have also been linked to system failure and catastrophic mission failure. See for example, Y. Boulghassoul, L. W. Massengill, A. L. Sternberg, and B. L. Bhuva, “Effects of Technology Scaling on the SET Sensitivity of RF CMOS Voltage-Controlled Oscillators,” IEEE Transactions on Nuclear Science, vol. 52, no. 6, pp. 2426-2432, December 2005 (hereinafter the Boulghassoul et al. article).
While SET mitigation and performance are crucial, one must consider power consumption and footprint as well. Ever increasing system complexity and size reduction require PLL solutions that consume minimal power and area while maintaining robust performance against SET phenomena yet still provide excellent performance. Mitigation of SET effects without negatively impacting performance is a great challenge, but it is critical to creating a dependable clock source for operation in harsh environments.
Design of large, complex digital systems requires low jitter clocking to ensure maximum timing margins. Flight time, setup and hold margins, and propagation delay consume a large portion of the timing window for synchronous signals, especially when routing over large areas or through various media. This leaves less and less time for clock jitter as a component of the timing margins as system speeds increase and systems grow. SET induced clock jitter and clocking errors must therefore be minimized or eliminated to ensure robust operation of any timing critical systems.